Electronic products in general and mobile devices in particular, have revolutionized the world over the past few decades with laptop computers, palm computers, wireless phones, digital cameras, to name just a few electronic products developed in recent years. Subsequent generations of such products are ever more compact, with improved features and functions. The integrated circuit (IC) and the more efficient packaging of the IC have played pivotal roles in enhancing the functionality and further miniaturization of these products.
As the IC of such products becomes ever more complex, the IC package continually requires more interconnections (pins or leads) with its surroundings to support increased logic and power requirements. At the same time, the IC package is required to be ever smaller and thinner to save space. Furthermore, the IC package is required to be highly thermally conductive to allow dissipation of the substantial amounts of heat generated by the operation of the IC. The IC package is also required to support the significantly increased processing speed and memory resources of the IC. A widely used technique to further improve system performance is to mount different ICs in close proximity, which also aids further miniaturization of course. In computers, for example, as the IC processing speed increases, the signal attenuation between the processor and the IC memory becomes of concern.
In consequence of the above, as the complexity and density of semiconductor devices has increased, the need for new and improved packaging techniques has also arisen. The so-called Multi-Chip Module (MCM) containing multiple devices in a single package is one such improved packaging technique. In an MCM, multiple semiconductor and passive devices are placed on a common substrate. Sealing this substrate and its ICs protects the devices and creates a powerful electrical component. This technique achieves a higher degree of device density and functionality than separately packaged semiconductor devices mounted on a printed circuit board. The higher density of the MCM translates to reduced data processing times within the ICs, while increasing memory and other required computing resources. Furthermore, by allowing the buses and interconnects of the MCM substrate to operate at the same speed and signal integrity levels as the IC itself, the partitioning of a complex IC into several simpler sub-units becomes a possibility. This approach not only allows cost reduction of the complex IC but typically shortens their time-to-market as well.
One common solution, already used in many portable electronic devices such as mobile phones and the like, is an MCM package that combines one or more processor chips, such as Digital Signal Processors (DSPs), with one or more memory ICs for enhanced functionality and performance.
More recently, multi-chip packaging methods have been proposed that provide for a plurality of chips deployed in more than one layer of a package. Examples include a stack of chips that are wire-bonded, flip chip bonded and/or otherwise bonded to one another and to the package substrate. It will be appreciated that the footprint of the multi-chip package is significantly reduced by this vertical orientation approach, but complex chip to chip interconnection techniques, such as for the stacked chip edge connection designs, may be required. For connecting chips to each other and to the package substrate, existing processing techniques sometimes require two or more methods, such as flip chip, wire bonding, and/or tape-automated bonding, for example. These and other currently available techniques may require a larger package height to accommodate multiple IC chips and wire-bond loops.
Another solution, which may be used together with stacked ICs, is to use cavity substrates, where a chip is fitted within the thickness of the substrate.
U.S. Pat. No. 4,682,414 to Butt, filed back in 1985, describes a multilayer circuitry having one element positioned within a recess or cavity, and a second element mounted on the surface. The multilayer circuitry typically consists of alternating metallic conductive and ceramic or glass dielectric layers that are manually built up onto a metallic substrate. As described in column 6 lines 20-28 however, the dielectric layer may comprise polyimide (Kapton). The metallic conductive layers are interconnected by drilling holes through the stack, which are then filled with copper, by electroless plating, for example. This requires holes to be drilled through the substrate, one at a time, in a stepwise manner, and is thus very time-consuming, expensive and inefficient. The technology used for forming the recess for the IC is not discussed.
U.S. Pat. No. 4,764,846 to Go describes a high density electronic package comprising stacked modules, wherein each cavity providing submodule may be formed by mounting a rectangle onto a base, or by etching out the cavity therefrom. The stacked structure has at least one interconnect plane that is adapted to be electrically connected to external circuitry. To connect to the outside world, electrical leads are formed on the surface of the substrate. The individual chip carrying carriers are laminated to form a stack.
U.S. Pat. No. 5,396,032 to Bonham describes a method and apparatus for providing electrical access to devices in a multi-chip module (MCM). Essentially a package body having a cavity is provided, and a plurality of ICs is stacked into the cavity. The package is designed to fit into a lead frame, and the gains in surface area saved by stacking ICs is offset by the large surface area required by the lead frame.
U.S. Pat. No. 5,495,394 describes three dimensional die packaging in multichip modules. Each substrate may include a cavity for mounting a chip therein, and has circuitry printed on the surface of the substrate. Within a multilayer stack, there is a plurality of signal layers, but each chip has all the circuitry thereto fabricated in a single layer. This planar requirement fundamentally limits the complexity of connections available to each chip. The possibility of interlayer connections by through plated vias is discussed (See Column 3 lines 5-10). It will be appreciated however, that such a connection technology is inherently expensive as each via is required to be drilled and then filled, and the drilling has to be done one via at a time, stepwise. This makes production time consuming and hence, expensive.
U.S. Pat. No. 5,579,207 to Hayden et al. describes another approach to three dimensional integrated circuit stacking. Ceramic sheets with cavities therein are stacked, and conduction between layers is accomplished by vias fabricated by drilling and filling with a conductive paste. The dielectric constants of most ceramics are relatively large, and the dielectric constant of alumina, the primary constituent of ceramic materials used in these substrates, is relatively high. This results in ceramic chip carriers exhibiting relatively low signal propagation speeds in comparison to substrates of other materials, particularly those with organic components, such as fiberglass-reinforced epoxy resin, polytetrafluoroethylene (Teflon), and the like.
U.S. Pat. No. 5,622,588 to Weber describes methods of making multi-tier laminate substrates for electronic device packaging. A method is disclosed for making multi-tier laminate substrates for electronic device packaging including providing a first laminating layer and a second laminating layer, each having a trace on a first side. These layers are laminated with a spacer layer and dielectric layers. A window is made in each of the spacer and the dielectric layers. After laminating the layers together, vias are formed. Then an opening is made in the first laminating layer that corresponds to the window openings in order to produce a cavity in the laminated structure for placing an electronic device therein.
The opening for the die cavity in the substrate is fabricated by milling (see Column 2 lines 34, 39, 45, column 7 line 42, column 9 line 43) and the vias are made through the laminated substrate and then plated (See column 3 lines 22-23), the fabrication technique being drilling (see column 8 line 27). Alternative processing in the form of laser based micromachining is also discussed (column 7 line 24).
U.S. Pat. No. 6,207,354 to Bhatt et al. describes a method of making an organic chip carrier substrate including a cavity for an IC. The substrate described is fabricated by lamination, with dielectric layers such as fiber reinforced epoxy being laid down onto a metallic substrate. The cavity is typically formed by a routing or profiling machine. However, other fabrication methods such as punching and drilling are also discussed (see column 6 line 16 to 31). These techniques are characterized by poor dimensional accuracy and low precision. Laser ablation is also mentioned.
U.S. Pat. No. 6,274,391 to Wachtler et al. (assigned to Texas Instruments) describes an HDI Land grid array packaged device having electrical and optical interconnects. A substrate is selected from any of a wide range of materials, and a cavity is formed or milled out (Column 8 line 48). After building up the structure, which may be accomplished by laminating dielectric layers and depositing metal layers thereupon, vias are formed. In addition to laser ablation, chemical processing such as liquid, gas or plasma processing is discussed (Column 9 line 18 to 25). It would appear therefore, that the use of etching to fabricate vias is considered. The manufacturing technique described includes forming a cavity in the substrate, inserting the semiconductor device into the cavity, and only then building up the layered structure. Finally, vias are formed by creating holes through the structure which may be subsequently filled.
U.S. Pat. No. 6,266,251 to Bassi et al. describes a cavity downward, ball grid array module having a cavity for absorbing excess chip adhesive. It does not relate to efficient inter chip vias.
U.S. Pat. Nos. 6,226,696 and 6,306,686 to Horton et al. (assigned to IBM) describe a method of fabricating an electronic package with interconnected chips. A cavity is formed right through a substrate, two chips are mounted in the cavity and then a heat sink is added. They do not relate to efficient inter chip vias either.
U.S. Pat. No. 6,492,253 to Chia et al. describes a method for programming a substrate for array type packages. The substrate is fabricated from a nonconductive material and vias are drilled there through and then filled with conductor. Such a connection technology is inherently expensive as each via is required to be drilled and then filled, and the drilling has to be performed stepwise, one via at a time. This makes production time-consuming and hence, expensive.
U.S. Pat. No. 6,507,107 to Vaiyapuri (Micron Technology Inc.) describes a semiconductor/printed circuit board assembly. One substrate supporting a semiconductor die is stacked upon another, and the connections there-between are by conductive lines (wires) that pass through hole in the substrate. To reduce the thickness of the stack, the mounting of semiconductor dies within cavities within each substrate is contemplated. However, methods of formation of these cavities are not discussed.
U.S. Pat. No. 6,558,978 to McCormick describes a “chip-over-chip” integrated circuit package, where chips are stacked using cavity-less semiconductor substrates. This approach will, of necessity, result in a relatively thick stack.
Published United States Application Number US 2003/0192171 to Fey et al. entitled “Space saving packaging of electronic circuits” describes an apparatus and packaging method for stacking a plurality of integrated circuit substrates which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits whilst facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing. The publication is directed to packaging techniques for electronic circuits and in particular to vertical stacking of a plurality of electronic circuits. Preferred embodiments of the chip stack include a cavity for containing and protecting surface mounted devices such as a crystal and the like. No description of the cavity production technique is given.
U.S. Pat. No. 6,781,243 to Li et al. (National Semiconductor Corporation) describes a leadless lead frame package substitute and stack package in which a semiconductor package is provided with an internal package formed in the cavity of the external leadless lead frame package (LLP). The internal package is a leadless lead frame package and provides a substrate for mounting one or more dies and passive devices to form the external LLP. By arranging the die and passive components on the internal package, higher chip density and a smaller form factor may be achieved.
WIPO Publication Number WO 2004/012266 to Figueroa et al. (Intel Corporation) entitled “Electronic package substrate with back side, cavity mounted capacitors and method of fabrication therefor” describes an electronic package, such as an integrated circuit package, that includes a cavity on the back side of the package, which is the same side on which connectors to a next level of interconnect are located. Contacts which enable one or more discrete capacitors to be electrically connected to the package are provided within the cavity. The package provides a very low vertical inductance path between the capacitors and an integrated circuit mounted on the front side of the package. As described on page 9 lines 31 to 32 thereof, in one embodiment the cavity is formed using a masking and etching process as known in the art.
U.S. Pat. No. 6,790,760 to Cohn et al. (Broadcom Corporation) describes a method of manufacturing an integrated circuit package. A multilayer substrate is proposed and once again, the vias are formed by drilling and plating.
U.S. Pat. No. 6,869,827 to Vaiyapuri (Micron Technology, Inc) entitled “Semiconductor/printed circuit board assembly, and computer system” describes a stacking method for a semiconductor die that involves forming topographic contacts extending from a second surface of an intermediate substrate to a first surface of a printed circuit board. Two or more chips, each mounted on a substrate are stacked into a layered structure, where the contact wires pass through openings in the intermediate substrates.
U.S. Pat. No. 6,861,750 to Zhao et al. describes a ball grid array package with multiple interposers wherein the various IC packages are mounted on stiffeners and stacked, and the vertical height of the stack may be reduced by using cavities, or openings, which are cutouts or notches (column 11 line 65, column 12 lines 3 and 16).
U.S. Pat. No. 6,896,553 to Zhao et al. (Broadcom Corporation) entitled “An enhanced die up ball grid array packages with two substrates” relates to a ball grid array package for high-speed integrated circuits that has a first substrate surface attached to a first stiffener surface, and a second substrate surface attached to a second stiffener surface. Of particular interest, in column 19 lines 55 to 60 thereof, in one embodiment, the openings for the passage of wire bonds are fabricated by an acid etch process. The central opening for the IC chip is fabricated by cutting or punching out however.
U.S. Pat. No. 6,882,042 to Zhao et al. (Broadcom Corporation) relates to a thermally and electrically enhanced ball grid array package. As described in column 5 lines 35 to 40, the substrate of the BGA package may comprise alternating metal layers and dielectric layers with conductive vias. The opening or window in the substrate, for chip mounting is punched out (See column 6 line 19, column 6 line 42 and Table 2 thereof).
U.S. Pat. No. 6,930,364 to Bruner describes a microelectronic mechanical system and method that creates a cavity in a silicon dioxide or silicon nitride substrate by sacrificial etching using a gas etching technique with a noble gas fluoride NGF2x.
U.S. Pat. No. 6,949,289 to Lawton et al. entitled “impregnated glass fiber strands and products including the same” is incorporated herein by reference. It describes, inter alia, usage of fiber reinforced composites as electronic support structures, as chip packages, PCBs and the like. Such FRCs may be copper clad (Column 89 lines 10 to 15). Vias are described as being fabricable by mechanical and laser drilling (see Column 54 lines 1-18).
U.S. Pat. No. 6,949,823 to Schott et al. describes a method and apparatus for high electrical and thermal performance ball grid array package, wherein the package is constructed from thick film ceramic and the cavity is fabricating by laser cutting.
U.S. Pat. No. 6,964,881 to Chua et al. (Micron Technology, Inc.) entitled “Multi-chip wafer level system packages and methods of forming same” relates to a packaging implementation providing a multichip multilayer system on a chip solution wherein greater integration of a plurality and variety of known good die (sic) contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. The substrate is typically a silicon wafer (Column 3 line 58) and the cavities are formed using an anisotropic silicon etching process (column 5 line 46). The stack build up may include alternating metal, e.g. copper (column 8 line 5) and dielectric layers. Vias or openings may be formed by etching (column 8 line 18). As shown in claim 1 (column 9 line 41) the cavities are formed on the top surface of the substrate (silicon wafer, see column 10 line 26) prior to build up of the laminate structure.
It will be appreciated that micromachining processes, such as drilling, milling, laser micro ablation and micro cutting, are processes that fabricate holes one hole at a time. The formation of vias and cavities one at a time in this manner is time consuming and hence, expensive. For mass production, where many packages are fabricated at once, such techniques are inherently unsuitable.
Thus, despite the developments described above, there is still a need for manufacturing processes and chip support structures, particularly cavity support structures that overcome the disadvantages of the prior art, and that are economical and particularly suitable for large scale manufacture.
Consequently, there is a need for an improved multi-chip package technology that increases package density, and improves performance, including increasing access speeds between chips by significantly reducing interconnect traces and via lengths, while not substantially increasing package height or the complexity of packaging processing techniques. To minimize production time and to optimize throughput, such a technology should avoid laser ablation, mechanical milling and drilling of vias, cavities and the like and having high yield, and excellent reliability.
In some applications it is desirable to separate different functionality such as memory and processing capabilities into two separate chips. To save space, which is often at a premium, and to facilitate further miniaturization, it is desirable to stack the memory and processor chips, one on top of the other. To facilitate this, a cavity substrate is desirable. The present invention provides a cavity substrate and a manufacturing technique thereof.